ILAng
  • Introduction
  • Getting Started
    • Installing ILAng
    • ILAng with CMake
    • ILAng with Python
    • ILAng in Docker
  • Modeling
    • ILA Model
    • Architectural States
      • Expressions
      • Uninterpreted function
    • Instructions
    • Hierarchical ILA
    • Conclusion
  • Synthesis
    • Writing Templates
    • Interfacing Simulators
    • Synthesis Results
    • Conclusion
  • Verification
    • Refinement Relation
    • Verification Target
    • Examples
    • Notes
  • Development
    • Release Notes
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  1. Verification

Verification Target

The verification target can be generated by create a VerilogVerificationTargetGenerator object. Some prerequisites are:

  1. ILAng should be configured to have the switch ILANG_INSTALL_DEV turned on.

  2. Include the header ilang/vtarget-out/vtarget_gen.h

The arguments of the constructors are:

  1. A list of paths to search for Verilog include files

  2. A list of Verilog design files

  3. The Verilog top module

  4. The variable mapping file (first part of refinement map)

  5. The instruction start/ready conditions (second part of refinement map)

  6. The output path of the verification targets

  7. The ILA model

  8. The choice backend (CoSA/JapserGold, the latter is not open-source and not included in the demo)

  9. (Optional) Target generator configuration

  10. (Optional) Verilog generator configuration

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Last updated 5 years ago

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