Verification Target

The verification target can be generated by create a VerilogVerificationTargetGenerator object. Some prerequisites are:

1. ILAng should be configured to have the switch ILANG_INSTALL_DEV turned on.

2. Include the header ilang/vtarget-out/vtarget_gen.h

The arguments of the constructors are:

1. A list of paths to search for Verilog include files

2. A list of Verilog design files

3. The Verilog top module

4. The variable mapping file (first part of refinement map)

5. The instruction start/ready conditions (second part of refinement map)

6. The output path of the verification targets

7. The ILA model

8. The choice backend (CoSA/JapserGold, the latter is not open-source and not included in the demo)

9. (Optional) Target generator configuration

10. (Optional) Verilog generator configuration